Develop a prototype with FPGA board and Conventional Camera;
Characterize the implementation of Counter Detection algorithm on FPGA and GPU;
Produce a Scientific Paper
Expected results:
Semester Thesis / Master Thesis
Following our internal evaluation, the candidate may be funded, on a merit basis, to present the results of the work at a world-class international conference
Voraussetzungen
Requirements:
Basic knowledge in Computer Vision, Electronics (FPGA), and HDL (Verilog or System Verilog)
